The present invention relates to a phase locked loop (PLL) circuit capable of generating an oscillation frequency based on an input signal such as a synchronizing signal, as well as to a reproducing apparatus incorporating that PLL circuit to produce a regenerative clock signal.
There exist reproducing apparatuses that deal with disk type storage media such as optical disks and magneto-optical disks and those that address tape type storage media such as magnetic tapes. Such reproducing apparatuses need a regenerative clock signal for bit extraction in decoding read data from the respective storage media. A clock signal synchronized with such read data is extracted generally by the PLL circuit. Some PLL circuits are known to be capable of automatically adjusting the center frequency of a voltage controlled oscillator (VCO).
FIG. 1 is a block diagram of a PLL circuit having such an automatic adjusting function. This is a PLL circuit that extracts a regenerative clock signal from an EFM (eight-fourteen modulation) signal in synchronism with that signal. The EFM is a modulation scheme adopted illustratively by CD (compact disk) players.
In FIG. 1, a crystal oscillator 41 has a built-in crystal resonator that outputs an oscillation frequency serving as a reference frequency. The reference frequency outputted by the crystal oscillator 41 is divided by a divider 42 having a predetermined dividing ratio. The divided output is inputted as a divided frequency signal S1 to a frequency counter 43.
Meanwhile, a voltage controlled oscillator (VCO) 44 has its oscillation frequency controlled by an output of an adder 53, to be described later. The output of the voltage controlled oscillator 44 is divided by another divider 45 having a predetermined dividing ratio. The output of the divider 45 is branched and inputted as a divided frequency signal S2 both to the frequency counter 43 and to a phase comparator 46.
The phase comparator 46 receives the divided frequency signal S2 as well as a binary EFM signal outputted by an EFM block 46. The EFM block 46 generates and outputs the binary EFM signal based on a reproduced RF signal read from a disk, not shown.
The phase comparator 47 compares the two input signals in terms of phase and supplies a detection output accordingly to a low-pass filter 47. The low-pass filter 48 filters the detection output from the phase comparator 47 and outputs an error signal S.sub.PO to the adder 53.
The frequency counter 43 compares the divided frequency signal S1 from the crystal oscillator 41 with the divided frequency signal S2 from the VCO 44 in terms of phase, and counts the frequency of the divided output of the VCO 44. A count result signal S.sub.FO of the frequency counter 43 is inputted to an adder 50 via a switch SW1. A reference value register 49 is set in advance with a reference value SR corresponding to a predetermined reference frequency based on an appropriate center frequency to be established for the VCO 44. The adder 50 subtracts the count result of the frequency counter 43 from the reference value in the reference value register 49. That is, the adder 50 provides error information on the divided frequency signal S2 from the VCO as counted by the frequency counter 43 with respect to the reference value SR corresponding to the center frequency.
The calculated output of the adder 50 is fed to a digital filter 51 for filtering. The output of the digital filter 51 is converted by a D/A converter 52 to an analog signal serving as a frequency error signal S.sub.FE that is sent to the adder 53.
The adder 53 adds up two inputs: the frequency error signal S.sub.FE from the D/A converter 52, and the error signal S.sub.PO acquired by the low-pass filter 48 filtering the compared output of the phase comparator 47. The output of the adder 53 is inputted as a controlled voltage Sc to the VCO 44.
With the PLL circuit constituted as described and incorporated illustratively in a reproducing apparatus, the following may occur: when the reproducing apparatus is turned on, scratches or dirt on the disk surface may typically result in focus servo errors or tracking servo errors, leading to the detection of a temporarily or perpetually dropped-out EFM signal that should be inputted to the phase comparator 47. In that case, the PLL circuit is switched to adjusting mode in which a center frequency for the VCO is readjusted.
In adjusting mode, the EFM signal to be inputted to the phase comparator 47 for comparison is switched to and replaced by an input signal fixed to the high or low level. This arrangement causes the EFM signal input side of the phase comparator 47 to be considered to have no signal. With no EFM signal received, the phase comparator 47 outputs no signal either.
At the same time, the switch SW1 is kept on in adjusting mode. In this state, the frequency counter 43 supplies the adder 50 via the switch SW1 with the frequency count result signal S.sub.FO representing the frequency counted on the basis of the divided frequency signals S1 and S2 coming from the crystal oscillator 41 and VCO 44 respectively. The adder 50 compares the input signal with the reference value from the reference value register 49. The added result is sent to the adder 53 eventually as the frequency error signal S.sub.FE.
In the case above, the adder 53 is not supplied with any output of the phase comparator 47. It follows that the controlled voltage Sc from the adder 53 is composed of the frequency error signal S.sub.FE alone. The VCO 44 is controlled only by a feedback loop involving the frequency error signal S.sub.FE in such a manner that the divided frequency signal S2 outputted by the VCO 44 may approach the reference value SR in the reference value register 49. That is the oscillation frequency of the VCO 44 is controlled to approach the center frequency predetermined as appropriate. When the oscillation frequency of the VCO 44 is controlled as described, a suitable center frequency is established for the VCO 44 in adjusting mode.
In normal operation mode that follows adjusting mode, the phase comparator 47 receives a binary EFM signal retrieved from the disk, while the switch S1 is held off. The adder 53 receives the error signal S.sub.PO from the low-pass filter 48, the signal having been obtained on the basis of the difference in phase between the EFM signal and the divided frequency signal S2 from the VCO 44. The frequency error signal S.sub.FE is the final value being held since the previous adjusting mode. This frequency error signal S.sub.FE is sent to the adder 53. The final value in adjusting mode is retained by a register (not shown) furnished in the digital filter 51.
The PLL circuit in normal operation mode thus controls the frequency of the VCO 44 variably by use of the controlled voltage Sc acquired by combining the error signal S.sub.PO with the frequency error signal S.sub.FE. The control operation ensures a zero phase difference between the divided frequency signal S2 from the VCO 44 and the EFM signal.
With the PLL circuit locked in normal operation mode, the divided frequency signal S2 from the VCO 44 is a regenerative clock signal in synchronism with the EFM signal. This regenerative clock signal is utilized as a processing clock signal by regenerative circuits as needed.
The phase comparator 47 is known to output a detection signal with a slight deviation from the actual phase difference because of characteristic variations intrinsic in the components making up the comparator. For example, suppose that when signals actually inputted to the phase comparator 47 have a zero phase difference therebetween, the phase comparator 47 outputs positive or negative detection pulses with a duty factor of 50% representing the zero phase difference. In that case, the duty factor of the output positive or negative pulses can actually develop a deviation attributable to constant errors or other characteristic variations intrinsic to the components constituting the phase comparator 47.
As a result, the EFM signal inputted to the PLL circuit of FIG. 1 in adjusting mode is regarded as nonexistent as described above. It is with no detection signal outputted by the phase comparator 47 that the center frequency is to be established. In such a setup for center frequency adjustment, any errors intrinsic in the phase comparator 47 are obviously not included.
Suppose now that adjusting mode in which the center frequency of the VCO 44 was established is then replaced by normal operation mode in which the phase comparator 47 receives the input EFM signal for phase comparison. In that case, the error signal S.sub.PO, i.e., detection output of the phase comparator 47, includes an error intrinsic to the comparator. It follows that the controlled voltage Sc from the adder 53 also includes the error of the phase comparator 47.
In normal operation mode, the PLL circuit operates with the error of the phase comparator 47 left included. The implicit error is interpreted by the PLL circuit as a phase difference. The PLL circuit, when operating under the influence of that error, can eventually develop a capture range deviation or a lock range variation.
In addition, the EFM signal may drop out temporarily due to scratches or dirt on the storage medium, causing normal operation mode to be replaced again by adjusting mode for readjustment. In such a case, the center frequency of the VCO 44 may shift.
These difficulties can worsen the error rate in effect during signal retrieval from the storage medium or lower the capability of recovery from temporary EFM signal drop-outs. The problems tend to detract from the reliability of the reproducing apparatus in the stage of its commercialization.